Static random access memories (SRAM) are widely used in digital systems to provide a high speed memory function in digital computers and other applications. In the current state of the art, single chip SRAMs typically include from eight thousand memory cells to up to half a million memory cells. Typical access times are on the order of 10 nanoseconds or more, with memory cycle times approximately twice this value.
In the present state of the SRAM art there is a continued need to increase the density of SRAM devices by reducing the size of the individual memory cells. However, a decrease in cell size must not occur at the expense of device operating speed or device reliability. In an SRAM, reliability includes a number of factors. One factor is the yield of SRAM devices in a given manufacturing process. Another factor is the ability to accurately store and recall data. Moreover, SRAM designs must be able to operate at high speeds and with data integrity over wide temperature ranges which are typically experienced by integrated circuit chips during their operation.
A typical SRAM design includes a pair of cross-coupled field effect transistors (FET) of first conductivity type for storing therein a binary "0" or "1". The cross-coupled pair of field effect transistors is typically a pair of N-channel FETs with their sources connected to ground potential, and the drain of the first transistor connected to the gate of the second transistor and the gate of the first transistor connected to the drain of the second transistor. A resistive load is also provided for each transistor in the cross-coupled pair, with each resistive load being serially coupled between a power supply voltage (V.sub.DD) and the drain of the respective cross-coupled transistor pair. Typically, a pair of "pass" transistors are also provided to facilitate reading and writing of data. A pass transistor is typically coupled to each drain of the cross-coupled transistor pair, with a word line being coupled to the gate transistor and a pair of bit lines connected to a respective one of the pass transistors.
The need to provide resistive loads for the cross-coupled transistor pair has heretofore limited SRAM device density and speed. The load resistors have also increased the standby power consumed by the device or the manufacturing reliability or repeatability. For example, in a well known SRAM design, a pair of N-channel cross-coupled FETs are connected to a pair of P-channel FET load resistors to eliminate standby power. Unfortunately, in order to fabricate P-channel FETs, a separate N-well diffusion is required in the integrated circuit substrate into which the P-type drain and source diffusions are placed. This N-well also must have a power supply voltage contact in addition to the ground contact needed for the substrate. These requirements both consume chip real estate and ultimately limit the density and speed of the SRAM.
The art has also attempted to replace the P-channel load transistors with load resistors. However, the resistance of these load resistors must be very large (for example, greater than 100 m.OMEGA.) to prevent excessive standby power from being dissipated by the load resistors. Accordingly, polycrystalline silicon ("polysilicon"), which is slightly doped above its intrinsic value, has been used to achieve the desired resistive value for the load resistors. Unfortunately, the grain size of the polysilicon must be well controlled in order to achieve the desired result. If not well controlled, the intrinsic carrier concentration in the polysilicon will vary widely from the bulk silicon single crystal value, thereby introducing wide manufacturing tolerances and preventing reliable, repeatable fabrication of the SRAM.
Other prior art techniques have used depletion mode, N-channel transistors for load resistors. Unfortunately, the use of N-channel depletion mode transistors leads to a yield problem in attempting to control the slightly conductive state of the channel.